NANDA Workshop

5-6 September 2022

The Imperial College HiPEDS Research Centre hosted an exciting 2-day workshop on Novel Architecture and Novel Design Automation (NANDA).

This brought together renowned experts in these two areas to present their latest advances and create a forum to spark new ideas.

Workshop details

Programme - Day 1

Monday, 5 September 2022

08:50 - Welcome

09:00 - NANDA: the Next Frontier

            Wayne Luk, Imperial College

09:30 - When Serverless Meets Servers

            Boris Grot, University of Edinburgh

10:00 - Dedicated Inter-FPGA Networks for Scalable Reconfigurable Computing

             Kentaro Sano, RIKEN

10:30 – BREAK

11:00 - Bringing Formal Methods to FPGAs

            John Wickerson, Imperial College

11:30 - What Interactive Theorem Proving Can Do For Verilog Hardware Development

            Andreas Lööw, Imperial College

12:00 - ROVER: RTL Optimisation via Verified E-graph Rewriting

            Samuel Coward, Imperial College and Intel

12:30 – LUNCH

14:00 - Co-designing a Language, Tool chain, and Architecture: Lessons Learnt from the POETS Project

            David Thomas, University of Southampton

14:30 - Efficient Deployment of CNNs under Resource Constraints

            Christos-Savvas Bouganis, Imperial College

15:00 - Towards a Formal Specification of Intel’s x86 Architecture

            Alastair Reid, Intel

15:30 – BREAK

16:00 - Extending Intel-x86 Consistency and Persistency

            Azalea Raad, Imperial College

16:30 - Precise-Event Sampling on x86 Architectures and Its Uses in Profiling Tools

            Didem Unat, Koç University

17:00 - Clio A Hardware-Software Co-Designed Disaggregated Memory System

            Yiying Zhang, UCSD

Programme - Day 2

Tuesday, 6 September 2022

09:00 - From C/C++ to Dynamically Scheduled Circuits

            Lana Josipović, ETH

09:30 - Architectural Support for Persistent Memory

            William Wang, Arm

10:00 - Vector Runahead for Indirect Memory Accesses

             Sam Ainsworth, University of Edinburgh

10:30 – BREAK

11:00 - Neural Processing Unit for Transformers and Hardware-Neural-Network Co-Design

            Thomas Chau, Samsung AI Centre

11:30 - Compiler IRs: The Gold of Computer Systems

            Tobias Grosser, University of Edinburgh

12:00 - Integrated Design and Verification: An Ounce of Prevention is Worth a Pound of Cure

            Carl-Johan Seger, Chalmers University of Technology

12:30 - Towards Ubiquitous Accelerators

            Mikel Luján, University of Manchester

13:00 – LUNCH

14:00 - Towards Cross-Domain Domain-Specific Compiler Architecture

            Paul Kelly, Imperial College

14:30 - Security as a Performance Principle: A Tale on Hardware/Software Codesign

            Lluis Vilanova, Imperial College

15:00 - The Entangling Instruction Prefetcher

            Alexandra Jimborean, University of Murcia

15:30 - Closing